The present invention relates to a Bipolar-CMOS (BiCMOS) logic circuit and, more particularly, to a BiCMOS logic circuit which is suitable for operation under low power supply voltage.
In recent years, with advancement in speed of operation of integrated circuits, the demand for BiCMOS logic circuits is increasing. In one type of BiCMOS logic circuit which is recently attracting attention, there are an NPN bipolar transistor and N-channel MOSFETs (hereinafter referred to as "NMOSs") which are connected with each other in series and have an output terminal disposed between them. In another type of a typical conventional BiCMOS logic circuit, a similar arrangement includes two NPN bipolar transistors which are connected with each other in series. Generally, an advantage of BiCMOS logic circuits resides in their ability to drive a large load capacitance. However, in both the types of conventional BiCMOS logic circuits, there is a problem or disadvantage in that their operation speed under low power supply voltage is low. Full description of such conventional BiCMOS logic circuits and the problems existing therein will be fully explained later.